MP29508

MP29508

Digital Multi-Phase Controller

Parameters 概要

出力レールの数
1
フェーズ数
6
VCC（最小）（V）
3.1
VCC（最大）（V）
3.5
Iq (typ) (mA)
38
Ishutdown (typ) (mA)
0.23
fsw（最小）（kHz）
120
fsw（最大）（kHz）
1500
インターフェイス
PMBus/I2C
プロセッサタイプ
ASIC
パッケージ（mm）
TLGA-48 (6x6)
グレード
Catalog

The MP29508 is a digital controller that supports high-current, multi-phase voltage regulators (VRs). The device works together with external power stages to make a current double rectifier (CDR). It can be configured for up to 6-phase operation to support 3 blocks of 48V to 1.8V CDR modules.

The MP29508 provides an on-chip non-volatile memory (NVM) to store and restore device configurations. Device configurations and fault parameters can be easily configured and monitored via the PMBus/I²C interface.

The device is based on a unique, digital, multi-phase, nonlinear control to provide a fast transient response to the load transient with minimum output capacitors. With only one power-loop control method for both steady state and load transient, the power loop compensation is very easy to configure.

It is available in a TLGA-48 (6mmx6mm) package.

機能と利点

Up to 6-Phase Digital Controller
PMBus/I²C Compliant (800kHz Bus Speed)
Pin-Configurable PMBus Address
Built-In Non-Volatile Memory (NVM) to Store Configurations
120kHz to 1.5MHz Switching Frequency (f_SW)
Up to 3 Blocks for CDR Modules
Automatic Slope Compensation
Selectable Open-Loop or Closed-Loop Speel Control
Supports Multi-Configuration for 6 Different Applications
Active Current-Sharing between Modules
Phase-to-Phase Active Current Balancing (ACB) with Configurable Offsets for Thermal Balance
Monitoring for Input (V_IN) Voltage, Output Voltage (V_OUT), Input (I_IN) Current, Output Current (I_OUT), Input (P_IN) Power, and Output Power (P_OUT)
V_IN Under-Voltage Lockout (UVLO), Output Over-Voltage Protection (OVP)/Under-Voltage Protection (UVP), Over-Current Protection (OCP), Over-Temperature Protection (OTP) with No Action, Latch-Off, and Hiccup Options
Auto-Records the Voltage Regulator (VR) Fault Type to the NVM
Digital Load-Line Regulation
Overclocking Mode by Adding Offset to V_OUT
Password Lock for Accessing Registers
Available in a TLGA-48 (6mmx6mm) Package