MPQ5613D-AEC1

MPQ5613D-AEC1

Automotive TFT LCD Bias Driver with Gate Voltage Shaping and VCOM Buffer, AEC-Q100 Qualified

Description

The MPQ5613D-AEC1 is an integrated power supply for an automotive TFT LCD bias. The device integrates a boost converter, a synchronous buck-boost inverter, an adjustable positive charge pump output, and an adjustable negative charge pump output for the gate voltages. It also includes a VCOM buffer and gate voltage shaping function to minimize the external components. The MPQ5613D-AEC1 is designed to power TFT LCD panels from a regulated 3.3V or 5V supply, or the 12V battery directly.

The VDDP can output a maximum 21.8V voltage, the VDDN can output a minimum -16.6V negative voltage, the VGH can output a maximum 35V voltage, and the VGL can output a minimum -15.9V negative voltage.

The I²C interface and configurable power-on sequences for VDDP, VDDN, VGH, and VGL make the IC suitable for different applications.

An internal soft-start function prevents input overload at start-up. The cycle-by-cycle current-limit protection for SWP and SWN reduces component stress.

Robust protections are designed to guarantee safe operation of the device. Protection modes include input under-voltage lockout (UVLO), cycle-by-cycle current-limit protection for SWP and SWN, over-temperature protection (OTP), under-voltage protection (UVP) for VDDP, VDDN, VGH, and VGL, output over-current protection (OCP) for VCOM, and output current-limit protection for VDDP.

The MPQ5613D-AEC1 is available in a tiny QFN-28 (4mmx5mm) package. It is available in AEC-Q100 Grade 1.

Features & Benefits

2.7 to 12V Operating Input Voltage (V_IN) Range
2A Current Limit for Boost Converter
2.5A Current Limit for Sync-Buck-Boost Inverter
250mΩ Low-Side MOSFET (LS-FET) for Boost, 200mΩ High-Side MOSFET (HS-FET), and 250mΩ LS-FET for Sync Buck-Boost
I²C Interface, One-Time Programmable (OTP) Memory for Registers
Configurable Switching Frequency (f_SW) Up to 3MHz and Spread Spectrum for Better EMI
Frequency Synchronization and Interleave (180°) Buck-Boost and Boost Control for Better EMI
Input and Output Disconnection
Configurable VDDP: 2.7V to 21.8V
Configurable VDDN: -0.7V to -16.6V
VDDP and VDDN Support Max 500mA of Continuous Load Current (Limited by the Cycle-by-Cycle Current-Limit Protection)
Configurable VGH: 5V to 35V, 50mA
Configurable VGL: 0V to -15.9V, 50mA
Configurable VCOM Buffer: VDDN + 2V to VDDP - 2V, 25mA
Gate Voltage Shaping with Configurable Falling Time and Minimum Level
High Efficiency
Configurable Power-On/Off Sequence
V_IN Under-Voltage Lockout (UVLO)
Under-Voltage Protection (UVP) for VDDP, VDDN, VGH, and VGL
Cycle-by-Cycle Current-Limit Protection for SWP and SWN
Over-Temperature Protection (OTP), Output Over-Current Protection (OCP) for VCOM
Output Current-Limit Protection for VDDP
Fault Flag
Available in AEC-Q100 Qualified Grade 1
Available in a QFN-28 (4mmx5mm) Package