AN145 - Multi-Mode PFC + Current Mode LLC Controller

Figure 1: HR1211 Block Diagram

2. TYPICAL APPLICATION CIRCUIT

Figure 2: Typical Application Circuit

3. POWER SUPPLY FUNCTIONS

The power supply section of the HR1211 includes a high-voltage current source (HVCS) for starting up the IC, a VREG regulator for powering the gate drivers, and a 3.3V regulator for powering the digital core. The HR1211 has monitor circuits and protection circuits to make the IC more robust.

3.2.1 Supplying VCC with External Voltage

The external voltage can be standby power or DC power. Typically, the VCC voltage should be above V_CCUVP2. To power up the IC normally when HVCS is charging VCC, a diode must be added to isolate the standby power from VCC (see Figure 7).

Figure 7: Supplying VCC with Standby Power

3.2.2 Supplying VCC with LLC Auxiliary Winding

For non-standby applications, VCC is supplied by the LLC auxiliary winding for higher efficiency. Figure 8 shows two types of auxiliary winding configurations: a half-wave rectifier and a full-wave rectifier. Typically, a full-wave rectifier has higher efficiency and produces a larger VCC if the turns of two windings are the same, thereby increasing efficiency at light load. However, the full-wave rectifier requires another winding and rectifying diode, which increases cost.

Figure 8: Supplying VCC with LLC Auxiliary Winding

3.2.3 VCC Current

The current consumed by VCC includes the V3.3 current, VREG current, and bias current of the internal circuit. The total current is the sum of these three currents.

In the duration of t0 to t2, and before V3.3 is enabled, the current of VCC is about 200µs. In the duration of when V3.3 is enabled and before the IC is enabled (t₂ to t₃ and t₇ to t₉), the current of VCC is I_{CC_START1}. Once the IC is enabled, the current of VCC is I_CC(NOR) in normal operation and I_{CC_BURST} at burst-off mode.

4.3 PFC Output Regulation

The PFC output voltage VBUS is regulated by the digital PI loop. If the accuracy of R_OUT1 and R_OUT2 in Figure 13 is 1%, the accuracy of VBUS is within 2.5%, considering the accuracy of ADC is about 0.6%.

To optimize the efficiency of the PFC, the HR1211 can auto-adjust the output voltage at different input voltage and output load conditions. For example, the output voltage can be set to be lower when the input voltage is lower. Figure 24 shows how to configure some parameters.

Figure 24: GUI Interface of Output Voltage Regulation

4.4 Burst Operation of the PFC

When the output load is decreasing, the PFC converter runs in burst mode operation. The level to enter burst mode is programmable and is set using the percentage of V_{COMP_FULL}.

4.7 PF Compensation

To meet EMI requirements, an X-cap is usually connected between the L and N lines, and there is also a high-voltage capacitor connected to the output of the bridge diode is always in parallel with a high-voltage cap. As shown in Figure 32, the input current will be distorted and shift ahead of the inductor current. The current flowing through C_Z (X-cap plus high-voltage cap after bridge) can be calculated with Equation (36):

$$i_{C_Z} (t) = C_{Z} \frac {dV_{in} (t)}{dt} = 2 \times \pi \times f_{line} \times C_z \times \sqrt 2V_{in_{rms}} \times cos (2 \times \pi \times f_{line} \times t)$$

Where f_LINE is the frequency of the input voltage.

Figure 32: Relationship of Input Current, C1 Current, and Inductor Current

This current causes a phase shift of input current at light load and worsens the power factors and THD. The HR1211 implements a digital triangular wave to compensate for I_CZ (see Figure 34).

Figure 34: Compensation with Triangular Wave

4.10 Programmable Digital Filter

4.10.1 Current Sense Filter

The HR1211 implements two programmable digital filters (csp filter and td filter) internally for noisy immunity improvement.

Both the csp filter and td filter are second-order filters and can be configured by the GUI (see Figure 42). The filter function is enabled when the button set is to “ON” and disabled when the button is set to “OFF”. There are 15 levels of bandwidth for each order filter which is selected flexibly according to practical applications.

Figure 42: Parameters of Programmable Digital Filter

4.10.2 Voltage Sense Filter

To enhance the anti-interference ability of the PFC output voltage sense, the HR1211 implements a programmable filter on FBP sensing. The cut-off frequency of the digital filter is programmable with three levels. With the voltage sense filter, the capacitor (C₃) parallel with R_out2 can be reduced, which can improve the dynamic response and improve the accuracy of overvoltage protection.

5. HB RESONANT FUNCTIONS

The half-bridge resonant converter (LLC) can achieve high efficiency with the benefit of zero voltage switching (ZVS). The HR1211 uses a patented current mode control method for LLC converter.

5.1 Current Mode Control

Figure 45 shows the LLC current mode control strategy by sensing CR and FBL voltage which determines the LLC switching frequency.

Figure 45: LLC Current Mode Control Strategy

5.2 LLC Operating Mode Control Strategy

For HB LLC topology, the switching frequency gets higher which lead to magnetization and switching losses increase at light load condition. To control the output voltage and limit power consumption, the HR1211 implements a skip mode operation in light load and a burst mode operation in extremely light load which greatly reduces the average switching frequency, thus reducing the magnetic losses.

5.2.2 Burst Mode Operation

As the load gets even lighter, to further limit the average switching frequency, a longer switch idle time will be inserted into the skip mode, which is called burst-mode operation.

5.2.2.2 Ultra-Low Power Mode

To further reduce the IC power consumption, the HR1211 implements ultra-low power mode during the burst-off period (both the PFC and LLC enter burst mode). In ultra-low power mode, the system clock is reduced to 1/10, some internal bias current shuts down. The total IC consumption is reduced to I_{CC_BRUST} (typically 1.8mA).

5.4 Adaptive Dead-Time Adjustment (ADTA)

The adaptive dead-time control function adjusts the dead time automatically, which allows the LLC converter to achieve high efficiency from light load to full load due to ZVS.

Figure 59 illustrates the possible dead time with ADTA logic. Note that there are three possible dead times: minimum dead time (t_DMIN), maximum dead time (t_DMAX), and adjusted dead time which value is between t_DMIN and t_DMAX. When the transition time of SW is smaller than t_DMIN, the logic prevents the gate of HG or LG until t_DMIN is reached. This can avoid any shoot-through of the high-side and low-side MOSFET. If the dead time is too long, it may lead to duty cycle loss and loss of soft switching. A maximum dead time tDMAX is set forcing the gate to switch on. Both t_DMIN and t_DMAX can be programmable in GUI.

Figure 59: Waveforms Demonstrate ADTA

5.5 Slope Compensation Function

For current mode control stability, a digital 4-bits programmable slope voltage V_{CR_SLOPE} is added on the sensed voltage V_CR to generate V_CS (see Figure 60).

Figure 60: Slope Compensation Waveform

5.7 LLC Resonant Tank Parameters Design

The online design tool is available here

8. LAYOUT

This section describes the key considerations of routing and placing key components on the layout.

Figure 74 shows an example of the GND connection in the single-layer board. PGND and GNDD are connected and make the ground area as large as possible under IC, and then connected tof the negative port of the bus capacitor directly.

Figure 74: Layout Example

9. DESIGN EXAMPLE

The EVB is designed for verification and evaluation of the performance of the HR1211. For details of the EVB, please refer to the EVB datasheet. 9.2 EVB

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