OPERATION
This device is a high-frequency, synchronous, step-down converter with built-in power MOSFETs. Figure 2 shows a block diagram of the part. It is available with a wide 3.3V to 45V input supply range, and can achieve up to 3A continuous output current per phase, or parallel for 6A total output current. It can also be paralleled for 4-phase and 6-phase operation. The device offers excellent load and line regulation over an ambient temperature range of -40°C to +125°C.
PWM Control
At moderate to high output current, the device operates in a fixed-frequency, peak current control mode to regulate the output voltage. An internal clock initiates a pulse-width modulation (PWM) cycle. At the rising edge of the clock, the high-side switch (HS-FET) turns on, and the inductor current rises linearly to provide energy to the load. The HS-FET remains on until its current reaches the COMP voltage, which is the output of the internal error amplifier. The output voltage of error amplifier depends on the difference of output feedback voltage and the internal high-precision reference, which decides how much energy should be transferred to the load. The higher the load current, the higher the COMP voltage will be. Both the feedback divider ratio and reference can be adjusted by the PMBus, which makes it easy to adjust for different output voltages.
When the HS-FET is off, the low-side switch (LS-FET) turns on immediately and remains on until the next clock cycle starts. During this time, the inductor current flows through the LS-FET. In order to avoid shoot-through, dead time so the HS-FET and LS-FET are not turned on at the same time.
If the current in the HS-FET does not reach COMP set current value in one PWM period, the HS-FET remains on, saving a turn-off operation.
Mode Selection (AAM and Forced CCM)
This device can work in light-load AAM or forced CCM mode, determined by the PMBus. AAM (advanced asynchronous modulation) mode is employed to optimize the efficiency during light-load or no-load conditions. Forced CCM can maintain a constant switching frequency and smaller output ripple, but has low efficiency at light load.
If AAM mode is enabled with load decreasing, the device first enters discontinuous conduction operation (DCM) and maintains a fixed frequency as long as the inductor current approaches zero. If the load is further decreased, or there is no load that makes the inductor peak current lower than the AAM peak current threshold set by the PMBus, the device enters sleep mode and consumes low quiescent current to further improve light-load efficiency. In sleep mode, the internal clock is blocked, and the device skips some pulses. Then the feedback voltage is below the reference, so VCOMP ramps up until the inductor peak current exceeds the AAM threshold. The internal clock resets, and the crossover time is taken as the benchmark of the next clock cycle. This control scheme helps achieve high efficiency by scaling down the frequency to reduce switching and gate driver losses (see Figure 3).
As the output current increases from a light-load condition, VCOMP and the switching frequency increase. If the output current exceeds the critical level set by VCOMP, the device resumes fixed-frequency PWM control.
When forced CCM is enabled, the device operates in a fixed-frequency peak current control mode to regulate the output voltage, regardless of the output current.
Internal Regulator
A 5V internal regulator powers most of the internal circuitries. This regulator takes VIN and operates in the full VIN range. When VIN exceeds 5.0V, the output of the regulator is in full regulation. Lower VIN values result in lower output voltages. The regulator is enabled when VIN exceeds its UVLO threshold and EN is high. In EN shutdown mode, the internal VCC regulator is disabled to reduce power dissipation.
For better thermal performance, BIAS mode can be selected by the PMBus. If VOUT is above 5V, VCC and the internal circuit are powered by VOUT.
Enable Control
EN is a digital control pin that turns the regulator, including the PMBus block, on and off. Drive EN high to turn on the regulator; drive it low to turn the regulator off. The EN threshold can be programmed by the PMBus. An internal 5MΩ resistor from EN to GND allows EN to be floated to shut down the chip.
Oscillator Frequency
The default frequency of this device is 500kHz, and it can be programmed from 300kHz to 2.5MHz by the PMBus. The frequency can also be set by a logic-level synchronous signal.
SYNC IN and SYNC OUT
The SYNC pin can be programmed by the PMBus to SYNC IN or SYNC OUT. When operating as SYNC IN, the internal oscillator frequency can be synchronized by an external clock via this pin. At start-up, the device first operates at the internal set frequency, and quickly synchronizes to the external clock once soft start is ready. Ensure the high amplitude of the SYNC clock is above 1.8V and the low amplitude is below 0.4V to drive the internal logic. The recommended external SYNC frequency range is 250kHz to 2.2MHz.
The device operates in forced CCM mode with fixed frequency when there is a SYNC clock, regardless of output current. A pulse longer than 200ns is recommended in application.
When the SYNC pin is set to SYNC OUT, the device outputs the internal clock with a 0° or 180° phase shift. With this function, two devices can operate in same frequency, but 180° out of phase, to reduce the total input current ripple so a smaller input bypass capacitor can be used.
Under-Voltage Lockout (UVLO)
The device has input under-voltage lockout protection (UVLO) to ensure reliable output power. If EN is active, the device is powered on when the input voltage exceeds the UVLO rising threshold, and is powered off when the input voltage drops below the UVLO falling threshold. The UVLO threshold can be set between 3.3V and 5.7V by the PMBus. This function prevents the device from operating at an insufficient voltage. It is a non-latch protection.
Soft-Start
The device has built-in soft start (SS), which ramps up the output voltage at a controlled slew rate when EN goes high, avoiding overshoot during start-up. When the chip starts, the internal circuitry generates a soft-start voltage that ramps up slowly. When the SS voltage (VSS) is below the internal reference (VREF), VSS overrides VREF as the error amplifier reference. When VSS exceeds VREF, VREF acts as the reference. At this point, soft start finishes and the device enters steady-state operation.
The SS time is internally set to 1ms as a default, and can also be set to 0.5ms, 2ms, or 4ms by the PMBus. When the output voltage shorts to GND, the feedback voltage is pulled low, and VSS is discharged. The part soft starts again when it returns to normal conditions.
Pre-Bias Start-Up
For this device, at start-up, if the output feedback voltage is greater than VSS (which means output has pre-bias voltage), neither the HS-FET or LS-FET turn on until VSS exceeds the feedback voltage.
Power Good Indicator
The device has power good (PG) indication. The PG pin is the open drain of a MOSFET. It should be connected to a voltage source through a resistor (e.g. 100kΩ). In the presence of an input voltage, the MOSFET turns on so that the PG pin is pulled to GND before soft start is ready. When the output voltage is within the default ±10% window of rated voltage, PG is pulled high after a delay (typically 30μs). If VOUT moves outside the default ±10% range with a hysteresis, the device pulls PG low to indicate a failure output status. Both the PG threshold and hysteresis can be programmed by the PMBus.
FAULT Indicator
The /FT pin is also an open drain of a MOSFET. It should be connected to a voltage source through a resistor (e.g. 100kΩ). /FT is pulled high in normal operation, and any fault or warning pulls this pin low to indicate a fault status, including input OVP, output OVP, SCP, and thermal shutdown.
Over-Current Protection (OCP)
The device has cycle-by-cycle, over-current limit control. The inductor current is monitored during the HS-FET on state. Once the inductor peak current exceeds the set current limit threshold, the HS-FET immediately turns off. Then the LS-FET turns on to discharge the energy, and the inductor current decreases. The HS-FET does not turn on again until the inductor current falls below the valley current limit. This function helps prevent the inductor current from running away and possibly damaging the components. Both the peak current and valley current threshold can be programmed by the PMBus.
When the peak current limit is triggered, the OCP timer starts immediately. The OCP timer can be set to 32, 64, 128, or 256 cycles by the PMBus. Reaching the current limit in each cycle of this OCP timer triggers SCP operation (hiccup as default), which is detailed in the following section.
Short-Circuit Protection (SCP)
When a short circuit occurs, the device immediately reaches its current limit. Meanwhile, the output voltage quickly drops to the under-voltage threshold (default is 50% of the setting output). The device considers this an output dead short, and directly triggers SCP operation. Three modes can be selected by the PMBus for SCP operation: hiccup as default, switching with non-hiccup, and latch-off.
In default hiccup mode, the device disables its output power stage and resets the soft-start voltage, then initiates a soft start procedure. The off time is determined by the soft-start time and hiccup duty, which can both be set by the PMBus. If the short-circuit condition remains after soft start ends, the device repeats this operation until the short circuit disappears and the output returns to the regulation level. This protection mode greatly reduces the average short-circuit current by periodically restarting the part to alleviate thermal issues and protect the regulator.
Over-Voltage Protection (OVP)
The device monitors the output voltage through the VOUT pin to detect output over-voltage conditions. When the output voltage exceeds the OVP threshold (default is 120% of the setting voltage), OVP mode is triggered. Three modes can be selected by the PMBus for OVP operation: disable as default, discharge, and latch-off.
The device also has optional input OVP. The threshold can be set to 28V or 34V. If VIN exceeds this threshold, the device stops switching. This is a non-latch protection; the device resumes normal operation once the input OVP is removed.
Thermal Shutdown
The device employs thermal protection by internally monitoring the IC temperature. This function prevents the chip from operating at exceedingly high temperatures. If the junction temperature exceeds the threshold (default 175°C), it shuts down the whole chip. This is a non-latch protection, and there is a default 25°C hysteresis. Once the junction temperature drops to about 150°C, the device resumes normal operation by initiating a soft start. Both the OTP threshold and hysteresis can be set by the PMBus.
Floating Driver and Bootstrap Charging
An internal, built-in bootstrap capacitor powers the floating HS-FET driver. When the voltage difference between BST and SW is less than the internal 5V bootstrap regulator, a PMOS pass transistor M1 connected from VIN to BST turns on to charge the bootstrap capacitor. The current path is through D1, M1, C4, L1, and C2 (see Figure 4). If VIN - VSW exceeds 5V, U1 will regulate M1 to maintain a 5V BST voltage across C4. Meanwhile, the external circuit must have enough voltage headroom to accommodate charging. A 10Ω resistor placed between SW and the BST capacitor is strongly recommended to reduce SW spike voltage.
As long as VIN is sufficiently higher than VSW, the bootstrap capacitor can be charged. When the HS-FET is on, VIN is about equal to VSW so the bootstrap capacitor cannot charge. The best charging period occurs when the LS-FET is on so that VIN - VSW is at its largest. When there is no current in the inductor, VSW equals VOUT, so the difference between VIN and VOUT can charge the bootstrap capacitor.
In higher duty cycle operation conditions, the internal charging circuit may not have sufficient voltage and time to charge the bootstrap capacitor. In this case, extra external circuitry can be used to ensure the bootstrap voltage is in the normal operation range.
Low-Dropout Operation (BST Refresh)
To improve dropout, the device is designed to operate at close to 100% duty cycle as long as the BST-to-SW voltage is greater than 2.5V. When the voltage from BST to SW drops below 2.5V, the HS-FET turns off using a UVLO circuit, which allows the LS-FET to conduct and refresh the charge on the BST capacitor.
In cases where the input voltage drops, the HS-FET remains on and close to 100% duty cycle to maintain output regulation, until the BST-to-SW voltage falls below 2.5V. Since the supply current sourced from the BST capacitor is low, the HS-FET can remain on for more switching cycles than are required to refresh the capacitor. Therefore, the effective duty cycle of the switching regulator is high.
The effective duty cycle during dropout of the regulator is mainly influenced by the voltage drops across the power MOSFET, inductor resistance, low-side diode, and PCB resistance.
PMBus Control and Default Output Voltage
When the device is enabled (EN = high and VIN > UVLO), the chip starts up to a default 5V output voltage. After that, the PMBus can communicate with the master. Once the PMBus receives valid output voltage set instructions, the output voltage is determined by the PMBus control.
The output voltage setting is set by adjusting the internal reference voltage and output feedback divider ratio. After the device receives a valid data byte of output voltage setting, it searches the corresponding value from the truth table, sends the command of adjusting reference and divider ratio, and finally outputs the right voltage.
CRC Protection
The integrity of OTP is checked after a power-cycle reset. Each time the registers read the OTP contents, the device performs a CRC check. If a CRC error occurs, the registers will try to read two more times. If the error still occurs, the register will read the next available OTP page. If there is no available OTP page, then the CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the appropriate bit is set in the STATUS_MFR_SPECIFIC command, and the ALERTB pin is pulled low.
PMBUS INTERFACE
PMBus Serial Interface Description
PMBus is a two-wire, bidirectional serial interface, consisting of a data line (SDA) and a clock line (SCL). The lines are externally pulled to a bus voltage when they are idle. Connecting to the line, a master device generates the SCL signal and device address, and arranges the communication sequence. The device interface is a PMBus slave that supports both fast mode (400kHz) and high-speed mode (3.4MHz), adding flexibility to the power supply solution. The output voltage, transition slew rate, and other parameters can be instantaneously controlled via the PMBus interface.
Data Validity
One clock pulse is generated for each data bit transferred. The data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can only change when the clock signal on the SCL line is low (see Figure 5).
Start and Stop Conditions
The start and stop conditions are signaled by the master device, which signifies the beginning and the end of the PMBus transfer. A start condition (S) is defined as the SDA signal transitioning from high to low while the SCL is high. A stop condition (P) is defined as the SDA signal transitioning from low to high while the SCL is high (see Figure 6).
Start and stop conditions are generated always by the master. The bus is considered busy after the start condition. The bus is considered free again after a minimum of 4.7µs after the stop condition. The bus stays busy if a repeated start (Sr) is generated instead of a stop condition. The start and repeated start conditions are functionally identical.
Transfer Data
Every byte put on the SDA line must be 8 bits long. Each byte must be followed by an acknowledge (ACK) bit. The acknowledge-related clock pulse is generated by the master. The transmitter releases the SDA line (high) during the acknowledge clock pulse. The receiver must pull down the SDA line during the acknowledge clock pulse, so that it remains stable low during the high period of the clock pulse.
Figure 7 shows the format that data transfers follow. After the start condition, a slave address is sent. This address is 7 bits long followed by an 8th data direction bit (R/W). A 0 indicates a transmission (write), and a 1 indicates a request for data (read). A data transfer is terminated always by a stop condition, generated by the master. However, if a master still wishes to communicate on the bus, it can generate a repeated start condition and address another slave without first generating a stop condition.
PMBus Update Sequence
The device requires a start condition, a valid PMBus address, a register address byte, and a data byte for a single data update. After receipt of each byte, the device acknowledges by pulling the SDA line low during the high period of a single clock pulse. A valid PMBus address selects the device. The device performs an update on the falling edge of the LSB byte.
Device PMBus Chip Address
The ADD pin can be used to program the PMBUS address. The device supports seven addresses for up to seven voltage rails through configuring the resistor value that connecting between the ADD pin and ground. When the master sends the address as an 8-bit value, the 7-bit address should be followed by “0/1” to indicate a write/read operation.
Table 1 shows the resistor values for different PMBus addresses.
Table 1: PMBus Address
| Resistor (kΩ) 1% |
Address |
| 0 |
21h |
| 12.5 + 25 |
22h |
| 12.5 + 50 |
23h |
| 12.5 + 75 |
24h |
| 12.5 + 100 |
25h |
| 12.5 + 125 |
26h |
| 12.5 + 150 |
27h |
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