MP2731 1-Cell Solar MPPT Charger Reference Design

Features

Applications

• Outdoor Solar Surveillance Cameras
• Outdoor Lighting
• E-Bike Battery Chargers

Block Diagram

Block Diagram

Related Solutions

This reference design is based on the following MPS solution:

MPS Integrated Circuit	Description
MP2731	Single-cell switching charger with I2C control and NVDC PPM

System Specifications

Parameter	Specification
Input voltage range	3.7V to 16V
System output voltage	Up to $V_{BATT}$ (about 3.6V) + 100mV
System output current	Up to 4.5A
Charge current	Up to 4.5A
Switching frequency	1350kH
Board form factor	63mmx63mmx3mm

Design

MP2731 Single-Cell Switching Charger

The MP2731 is a 4.5A, highly integrated, switch-mode battery charger with NVDC power path management for a single-cell Li-ion or Li-polymer battery.

Inductor Selection

Inductor selection is a tradeoff between cost, size, and efficiency. From a practical standpoint, the inductor ripple current should not exceed 30% of the maximum load current under worst-case conditions. If the MP2731 operates with a 5V input voltage, the maximum inductor current ripple occurs after precharge, and when constant current (CC) charge begins. The inductance can be estimated with Equation (1):

$$ L= \frac { V_{IN} - V_{SYS} }{ \Delta I_{L\_MAX}} \frac {V_{SYS}}{V_{IN}\, x \, f_{SW}(MHz)}(\mu H)$$

Where $V_{IN}$ is the input voltage, $V_{SYS}$ is the system voltage, $f_{SW}$ is the switching frequency, and $\Delta I_{L\_MAX}$ is the maximum inductor ripple current, which is about 30% of the CC charge current.

The peak current can be calculated with Equation (2):

$$I_{PEAK} = I_{LOAD(MAX)}\, x\, \left(1+ \frac{\%ripple}{2}\right)(A)$$

The MP2731 has a maximum charge current of 4.5A, but the actual charge current cannot reach this value for the input current limit. For most applications, the maximum inductor current ripple is set to 0.5A with a 5V input voltage, so the inductor is $1.5\mu H$. For small applications, select a $1.0 \mu H$ inductor with a low DC resistance to optimize efficiency.

System Capacitor Selection

To ignore the ESR of the output capacitor, use a small ceramic capacitor with a lower ESR. The output voltage ripple can then be estimated with Equation (3):

$$\Delta r = \frac{\Delta V_{SYS}}{V_{SYS}} = \frac {1-{V_{SYS}\over V_{IN}}}{8\,x\,C_{SYS}\,x\,{f_{SW}}^2\,x\,L}$$

To guarantee the ±0.5% system voltage accuracy, the maximum output voltage ripple must not exceed 0.5% (e.g. 0.1%). The maximum output voltage ripple occurs at the minimum system voltage and the maximum input voltage.

If $V_{IN} = 5V, V_{SYS} = 3.7V, L = 1\mu H, f_{SW} = 1.35MHz$, and $\Delta r = 0.1%,$ the output capacitor can be calculated with Equation (4):

$$C_{SYS} = \frac {1-{V_{SYS}\over V_{IN}}}{8\,x\,{f_{SW}}^2\,x\,L\,x\,\Delta r}$$

In this example, choose a $22\mu F$ ceramic capacitor.

MPPT Theory

The output power from a solar panel is determined by several factors: the irradiance level, the operating voltage and current of the panel, and the load. There is a maximum power point where the solar panel outputs optimal power to the system (see Figure 3). Maximum power point tracking techniques, such as perturb-and-observe (P&O) or incremental conductance methods, ensure that the solar panels operate at MPPT under conditions where the irradiance changes.

Figure 3: Solar Panel P-V and I-V Curve

In the power-based P&O MPPT algorithm, the power-to-voltage derivative $(dP_O/dV_O)$ of a solar panel is used as a tracking parameter. Calculate when MPP is reached using Equation (5):

$$\frac{dP_O}{dV_O}=0$$

Where $P_O$ is solar panel output power, $V_O$ is solar panel output voltage.

MPPT Software Implementation

The P&O MPPT algorithm is implemented in a 20-pin, 8-bit MC96F1206 MCU from ABOV Semiconductor. To communicate with the MP2731, the I²C peripherals in the MCU are activated. Figure 4 shows the system-level software flow.

Figure 4: System-Level Software Flowchart

Note:Before updating I_OFFSET, turn off other devices connected at the MP2731’s SYS pin to ensure that I_OFFSET is calibrated correctly

The MCU enters sleep mode if VIN experiences an input power failure. If VIN is sufficient, the INT interrupt signal is sent to wake up the MCU. Then the MCU reads the MP2731 registers and initiates the registers (see Table 1).

Register Address	Value (Hex)	Value (Bin)	Description
0x00	0x7F	0111 1111	Sets the input current limit to 3.25A (maximum).
0x02	0xDC	1101 1100	Automatic input current optimization is disabled.
0x03	0x50	0101 0000	ADC continuous conversion is enabled.
0x08	0x84	1000 0100	Termination is enabled, and WTD and safety time are disabled.
0x0B	0xC0	1100 0000	USB detection is disabled.

By setting the input current limit to its maximum value, the panel voltage is controlled only by the input voltage limit loop. By adjusting the input voltage limit loop reference, the PV panel’s voltage can be adjusted. After initializing the MP2731, read the ADC initial value, and then enable charging.

If VIN_STAT is not equal to 1, increase VIN_REG by one unit, and then continue to go back to the previous VIN_STAT value. If VIN_REG reaches its maximum limit and VIN_STAT is still is not equal to 1, gradually decrease the charging current and return to the previous VIN_STAT value.

If VIN_REG set has reached its limit, the ICC set has a minimum at the same time. However, if VIN_STAT still is not equal to 1, the MCU goes into sleep mode. Meanwhile, the MP2731’s charging is disabled until the INT interrupt wakes the MCU.

If the PV panel is partially covered and a local MPP can be tracked using a conventional P&O MPPT algorithm, then the MCU initiates a scan every time the input voltage flag changes. To find the optimal power point, the MCU adjusts the input regulation voltage reference of the MP2731 with a 100mV step from 50% of the panel’s open-circuit voltage (V_OC) to 80% of V_OC.

After the initial scan, the PV panel operates at the maximum power point. To continue tracking the optimal point under varying load and irradiance conditions, the P&O algorithm runs every 256ms on the MCU (see Figure 5).

Figure 5: P&O MPPT Algorithm

Figure 6: Battery Charger with MPPT Schematic

BOM

Ref	Qty	Value	Package	Part Number	Manufacturer
C1, C8, C10	3	1μF	0603	GRM188R71E105KA12D	muRata
C2	1	4.7μF	0805	GRM21BR61E475KA12L	muRata
C4	1	100nF	0603	GCM188R71C104KA37D	muRata
C5	1	470nF	0603	GRM188R61E474KA12D	muRata
C7	1	10μF	0603	GRM188R61C106KAALD	muRata
C9	1	10μF	0805	GRM21BC81E106KE11L	muRata
C12	1	4.7μF	0805	GRM21BR61E475KA12L	muRata
C3	1	NC	1206		muRata
C6	1	NC	0603		muRata
L1	1	1uH	SMD	HTEP32251B-1R0MIR-89	Cyntec
LED1	1	BL-HUF35A-TRB	0805	BL-HUF35A-TRB	BRIGHT LED
R1,R2	2	2kΩ	0603	RC0603FR-072KL	Yageo
RILIM	1	30.9kΩ	0603	RC0603FR-0730K9L	Yageo
RT2	1	15kΩ	0603	RC0603FR-0710KL	Yageo
RT1, R8, R9	3	10kΩ	0603	RC0603FR-0710KL	Yageo
R3, R6, R10, R11, R4	5	0Ω	0603	RC0603FR-070RL	Yageo
R5	1	100kΩ	0603	RC0603JR-07100KL	Yageo
JP1	1		Header, 100mil, 3 x 1
JP2	1		Header, 100mil, 2 x 1
P1	1		5x2 shrouded header
GND, VPMID, DP, DM, VIN, VBATT, VSYS, SW, BST, STAT	10		Test point
VIN, PGND, VBATT, PGND, PGND, VSYS	6		2mm
U1	1		FCQFN (3.5x3.5mm)	MP2731GQC	MPS
U2	1	NC	7.5mmx 2.45mmx5mm
U3	1		QFN-20 (3mmx3mm)	MC96F1206USBN	ABOV

PCB Layout

PCB layout is critical for stable operations. For the best results when designing the general switching design, refer to Figure 7 and follow the guidelines below:

• Route the power stage adjacent to the grounds.
• Minimize the high-side switching node (SW, inductor) trace lengths in both the high-current paths and the current-sense resistor trace.
• Keep the switching node short and route it away from all small control signals, especially the feedback network.
• Place the input capacitor as close as possible to the PMID and PGND pins.
• Place the output inductor close to the IC, and connect the output capacitor between the inductor and PGND of the IC.
• For high-current applications, the pins for the power pads (IN, SW, SYS, BATT, and PGND) should be connected to as much copper in the board as possible. This improves thermal performance because the board conducts heat away from the IC.
• Connect a ground plane directly to the return of all components through via holes.
• If possible, place via holes inside the PGND pads for the IC.
• It is recommended to use a star ground design approach to keep circuit block currents isolated (highpower/ low-power, small-signal), which reduces noise coupling and ground-bounce issues. A single ground plane for this design gives good results. With this small layout and a single ground plane, there is no ground bounce issue, and having the components segregated minimizes coupling between signals and stability requirements.
• Pull the connect wire from the MCU (I2C) far from the SW mode and copper areas.
• Place SCL and SDA in close parallel.

Figure 7: Recommended PCB Layout Top Layer (Red) and Bottom Layer (Blue)

Test Results

Figure 10: Charge Efficiency (12V Panels with Different Power)

Time Domain Waveforms